Verilog register output: reg or wire?

If I want to model a simple register I would expect to have an internal 'reg' element to hold the value and I would connect this with a 'wire' output. The reg drives an internal output. However, I've looked up several examples and most use an output of type 'reg'. I don't understand why you would do that. Aren't you storing the value in two places this way? Is there a difference in behavior?

1 Answer 1

The way to choose how to declare your signal is not by how it will be physically instantiated, but by how you will syntactically assign its value.

If the signal is driven by assignments in a procedural block (a block beginning with always or initial ), then it must be declared as reg .

If the signal is driven by continuous assignment (an assign statement) or is the output of a module instance, then it must be declared as wire (or one of its variants like wor or wand ), or as an output without the reg qualifier.

A reg signal might be physically the output of either a latch or a flip-flop or of combinatorial logic (for example, there's a very common way of inferring a combinatorial multiplexer using an always block). A wire might be physically the output of a latch or a flip-flop or combinatorial logic (for example if the flip-flop is within a submodule).